FPGA Based Hardware Implementation of Simple Dynamic Binary Neural Networks

Abstract

This paper studies hardware implementation of a simple dynamic binary neural network that can generate various periodic orbits. The network is characterized by local binary connection and signum activation function. First, using a simple feature quantity, stability of a target periodic orbit is considered. Second, using a FPGA board, a test circuit is implemented. The signum activation function is realized by a majority decision circuit and the binary connection is realized by switches and inverters. The circuit operation is confirmed experimentally.