We present several new compiler techniques employed by our interprocedural parallelizing research compiler, Panorama, to improve loop parallelization and the efficiency of memory references. We first present an overview of the compiler and its associated memory architecture simulation environments. We then present an interprocedural array dataflow analysis, using guarded array regions, for automatic array privatization, an interprocedural static profile analysis, and a graph reduction algorithm for parallel task assignment and data allocation which aims at reducing remote memory references while maintaining loop parallelism.
CITATION STYLE
Nguyen, T., Gu, J., & Li, Z. (1996). An interprocedural parallelizing compiler and its support for memory hierarchy research. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1033, pp. 96–110). Springer Verlag. https://doi.org/10.1007/bfb0014194
Mendeley helps you to discover research relevant for your work.