An extended diagonal mesh topology for network-on-chip architectures

Abstract

This paper proposes an extended diagonal mesh (XDMesh) topology for network-on- chip (NoC) architectures to reduce latency and energy consumption for fast and low- power communication among remote nodes by including diagonal links in the network. In addition, we compare the performance of the proposed XDMesh with conventional state- of-the art topologies, including mesh, extended-butterfly fat tree (EFTI), and diametrical mesh, in terms of throughput, latency, energy consumption, and area overhead. Experimental results indicate that XDMesh outperforms the conventional topologies in terms of throughput and latency by varying the number of virtual channels and injection rate. Moreover, XDMesh achieves 46.28%, 35.29% and 19.37% lower energy consumption than EFTI, mesh, and diametrical mesh topologies, respectively, and 9.29%, 31.28%, and 15.23% lower silicon area, respectively.