Design and Implementation of Logarithmic Multiplier Using FinFETs for Low Power Applications

Abstract

In all processing systems, multiplication is one of the computation-intensive operations demanding more resources. Hence, multiplication operations demand more time, power and resources. One of the better solutions is Mitchell’s algorithm. Mitchell-based logarithmic multiplier is used as alternative approach which improves the speed, at the cost of accuracy. This paper presents the logarithmic multiplier implementation using the FinFETs. The hardware level simulation is done in Cadence Virtuoso using 18 nm technology. Comparison of power consumption of logarithmic multiplier using MOSFETs and FinFETs is presented. A 93.69% power reduction is seen in the proposed design as compared with the previous work.