Stacked high-ε gate dielectric for gigascale integration of metal-oxide-semiconductor technologies

Abstract

Advances in lithography and thinner SiO2 gate oxides have enabled the scaling of metal-oxide-semiconductor technologies to sub-0.25 μm feature size. A major hurdle in the gate dielectric scaling using conventional thermally grown SiO2 has been excessive tunneling that occurs in ultrathin (<25Å) SiO2. High dielectric constant materials such as Ta2O5 have been suggested as a substitute for SiO2. However, these materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta2O5 interface trap states, and low silicon interface carrier mobilities. This letter summerizes an elegant solution to these issues through synthesis of a thermally grown SiO2(15Å)-Ta2O5(30Å)-SiO 2(5-10Å) dielectric with improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold, saturation, and drive currents.