This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical verification. Experimenting with the STARI circuits, the proposed approach shows its effectiveness. © Springer-Verlag 2004.
CITATION STYLE
Pradubsuwun, D., Yoneda, T., & Myers, C. (2004). Partial order reduction for detecting safety and timing failures of timed circuits. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 3299, 339–353. https://doi.org/10.1007/978-3-540-30476-0_28
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