The return of power gating: Smart leakage energy reductions in modern out-of-order processor architectures

Abstract

Leakage power has been a significant concern in power constrained processor design as manufacturing technology has scaled down dramatically in the last decades. While power gating has been known to deliver leakage power reductions, its success has heavily relied on judicious power gating decisions. Yet delivering such prudent decisions has been particularly challenging for out-of-order processors due to the unpredictability of execution order. This paper introduces an intelligent power gating method for out-of-order embedded and mobile processor execution units by monitoring and utilizing readily available hints on the pipeline. First, we track the counts of different instruction types in the instruction queue to identify the execution units slated to remain idle in the near future. As the presence of an instruction is not a definite indicator of its execution start due to stalls, our second guidance improves the accuracy of the first approach by tracking the stalling instructions in the instruction queue due to memory dependencies. While tracking IQ content delivers dramatically better results than the state-of-the-art timeout-based methods in the literature with 48.8% energy reductions, the memory-aware guidance boosts energy savings up to 72.8% on average for memory intensive applications.