Silicon photonics research and manufacturing using a 300-mm wafer platform

Abstract

After 15 years of research, silicon photonics has now reached a sufficient level of maturity at the device level to be implemented into low-cost optical communication products. In this chapter we review the challenges of the industrialization of silicon photonics in 300 mm facilities, using mainstream CMOS methodologies. We first review the challenges of a sustainable electronic and photonic integration allowing the production of low-cost chips for the current 100G generation but also for the future 400G and beyond. Next, the industrial testing strategy and the design of test circuits allowing an efficient process monitoring are discussed. The industrial process integration scheme of optical components on 300 mm wafers is then described, followed by the device model strategy, which is a key element in order to make the link between the photonic design kit and the process. Finally, further R&D efforts in 300 mm allowing new functionality for the longer term Si photonics development are discussed. As examples, the integration of several Si etching levels, the demonstration of smart SOI substrates feasibility for improved coupling efficiency, and integration of ring modulator are detailed.