An enhanced trace scheduler for SPARC processors

Abstract

In this paper an enhanced trace scheduler implementation is described which targets processors with moderate support for parallelism and medium size register file such as the SPARC processors UltraSPARC(rtm) II and UltraSPARC(rtm) III. The enhanced trace scheduler is a global instruction scheduler, which identifies and exploits the available instruction level parallelism in a routine, contributing to performance improvement for UltraSPARC processor systems. The enhanced trace scheduler is part of the Sun Forte 6 update 2 product compilers for UltraSPARC II and UltraSPARC III processors. The enhanced trace scheduler, in exploiting the available instruction level parallelism, attempts to address issues such as register pressure, speculation and the amount of compensation code. © Springer-Verlag 2003.