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Book Chapter

3D-MAPS: 3D Massively Parallel Processor with Stacked Memory

  • Lim S
Springer New York, (2013), 537-560
DOI: 10.1007/978-1-4419-9542-1_20
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Abstract

This chapter describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology, and a two-tier 3D stacking...

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Lim, S. K. (2013). 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory. In Design for High Performance, Low Power, and Reliable 3D Integrated Circuits (pp. 537–560). Springer New York. https://doi.org/10.1007/978-1-4419-9542-1_20

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