This paper describes a novel approach for generating asynchronous circuits from HDL specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput constraints, and minimizing area. The method enables a form of automatic re-pipelining in which the throughput of the resulting design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles. © 2011 Springer-Verlag.
CITATION STYLE
Dimou, G. D., Beerel, P. A., & Lines, A. M. (2011). Performance-driven clustering of asynchronous circuits. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6951 LNCS, pp. 92–101). https://doi.org/10.1007/978-3-642-24154-3_10
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