Design and Implementation of Multi-level CIC Filter Based on FPGA

Abstract

The integral comb (CIC) filter is an efficient filter which is widely used in the digital down-conversion and up-conversion of wireless communication technology. However, the level width of each register of the traditional structure is fixed, and the low frequency signal can cause high frequency operation bandwidth and waste the shortage of computer hardware resources. This paper, by using Hogenauer “cut off” theory on each level of output bits wide truncated, improve the performance of CIC filter, through a cascade of multiple single stage CIC filter to optimize its structure, build the multi-stage CIC filter; At the same time using FPGA technology is strong, good extensibility and occupies less hardware resources, the characteristics of low cost, high reliability, using Verilog HDL language design the various modules, the final model of multistage CIC filter based on FPGA design, not only save the hardware resources, also make the CIC filter each register bits wide variable. The model was simulated by Modelsim and downloaded to the EP2C35F672C6 of Altera DE2 as the target chip verification, which met the design requirements.