Hardware implementation of chaos based cipher: Design of embedded systems for security applications

Abstract

In the information and communication security fields, system designers are faced with many challenges in both the trade-off cost/performance/power and architecture design. This is especially true for embedded system designs, often operating in nonsecure environments, while at the same time being constrained by such factor as computational capacity, memory size, and in particular power consumption. One challenge is the design of hardware architecture in order to obtain the appropriate security and the best tradeoff between hardware resources and the best throughputs rate for embedded applications. This chapter broadly outlines a disciplined approach to design and implementation 3D chaotic systems as Lorenz, Lü, Colpitts, Chen systems and so in embedded applications. The approach combines the numerical resolution method paradigm of 3D differential equations characterizing some chaotic systems with the design hardware architecture paradigm. The model of Runge-Kutta's numerical method to resolve 3D chaotic system requirements used as key generator for data encryption applications is detailed. This chapter describes this approach and presents a case study where the Lorenz's chaotic system is implemented on a FPGA Chip. © 2011 Springer-Verlag Berlin Heidelberg.