Memory based multiplier design in custom and FPGA implementation

Abstract

The modern real time applications like signal processing, filtering, etc., demands the high performancemultiplier design with fewer look up tables in FPGA implementation. This paper proposes an efficient look up table based multiplier design for ASIC as well as FPGA implementation. In the proposed technique, both the input operands of the multiplier are considered as variables and the proposed LUT based multiplier design is compared with other schemes like LUT counter, LUT of squares and LUT of decomposed squares based multiplier designs. The performance results have shown the proposed design achieves better improvement in depth and area compared with existing techniques. The proposed LUT based 12×4-bit multiplier achieves an improvement of 34.61% in depth compared to the counter LUT based architecture. The 16×16-bit proposed LUT based multiplier achieves an improvement factor of 76.84% in the circuit depth over the square LUT based multiplication technique using 45 nm technology.