Design and fabrication of a microprocessor using adiabatic CMOS and Bennett clocking

Abstract

This paper will describe the design and implementation of a MIPSbased microprocessor using Bennett clocking to implement reversible logic. In Bennett clocking the clock signals form a “cascade” that moves information forward through logic gates in the compute phase, and then recovers energy during a decompute phase, forming a reversible logic circuit. New logic design and verification tools were developed, using structural Verilog and extensions to ModelSim to address the issues of adiabatic clocking, tools that are currently unavailable in commercial packages. The microprocessor is based on a simplified version of the MIPS architecture. After verification by our design tools it was then implemented using CMOS standard cells based on split-level charge recovery logic. The final design contains approximately 5700 transistors, and is currently being fabricated at MOSIS.