This paper describes most recent development and demonstration of a VCSEL-based smart pixel array (SPA) technology for chip-to-chip interconnect. This technology is based on Honeywell's commercial successful 850nm VCSEL components, incorporates both monolithic and hybrid integration techniques, and aims to address anticipated interconnect bottleneck in networking interconnect fabric and between processors and memories. Following features of this technology makes it not only technically feasible but also practically viable for system insertion in very near future. First, new generating of oxide VCSEL technology provides key characters that high density 2D optical interconnect systems desire, such as high speed, high efficiency, low power dissipation and good array uniformity. Secondly, monolithically integration VCSEL and photodetector provides system with flexible bi-directional optical I/O solutions, and advantages in adopting new system architectures. Third, the 2D-optoelectronic array can be seamlessly merged with state-of-the-art Si-based VLSI electronics, and micro-optics using hybrid integration techniques such as solder bump bonding and wafer scale integration. Last, and perhaps most importantly, all of our technology implementations follow the guideline of being compatible with mainstream and low cost manufacturing practices. Device performance characteristics, integration approach, and results of up to 34x34 SPA prototype demonstration will be presented.
CITATION STYLE
Liu, Y. (2000). VCSEL based smart pixel array technology enables chip-to-chip optical interconnect. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1800). Springer Verlag. https://doi.org/10.1007/3-540-45591-4_155
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