Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior Art

  • Meinerzhagen P
  • Teman A
  • Giterman R
  • et al.
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While 6-transistor (6T)-bitcell static random-access memory (SRAM) macrocells are the mainstream solution for embedded memories in very large scale integration (VLSI) systems-on-chip (SoCs), as discussed in Chap. 1, embedded dynamic random-access memory (eDRAM) macrocells are an interesting area-efficient alternative. The conventional eDRAM bitcell uses a dedicated storage capacitor to store information in the form of electric charge. It further uses a single metal-oxide-semiconductor field-effect transistor (MOSFET) to access the storage capacitor for read and write operations. Unfortunately, such conventional 1-transistor-1-capacitor (1T-1C)-bitcell eDRAM requires special processing steps to manufacture high-density stacked or trench capacitors. It is therefore not directly compatible with standard digital complementary metal-oxide-semiconductor (CMOS) tech-nologies [16] and not readily available for integration with logic in all process flavors and nodes. As opposed to conventional 1T-1C eDRAM, gain-cell (GC) based eDRAM (GC-eDRAM) is fully compatible with mainstream digital CMOS technologies, since it is built exclusively from MOSFETs and, optionally, the readily available metal stack and vias. MOSFETs are used as access transistors and as MOSCAPs. Metal layers and vias can be used to enhance the storage node capacitance. As such, GC-eDRAM is an interesting alternative to 6T-bitcell SRAM and 1T-1C eDRAM, since it combines many of the advantages of SRAM (e.g., the compatibility with digital CMOS technologies) and 1T-1C eDRAM (e.g., higher storage density than SRAM), while it avoids most of the drawbacks of SRAM (e.g., the large bitcell) and of 1T-1C eDRAM (e.g., the destructive read, write-back operation, and extra cost for special process options). Thanks to its compatibility with standard digital CMOS technologies, GC-eDRAM macrocells can readily be integrated with any digital system at no additional manufacturing cost for special process options, as opposed




Meinerzhagen, P., Teman, A., Giterman, R., Edri, N., Burg, A., & Fish, A. (2018). Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior Art. In Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip (pp. 13–26). Springer International Publishing.

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