Effect of bias temperature instability on soft error rate

Abstract

Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. With the decreasing of device sizes the aging effect cannot be ignored during soft error rate (SER) estimation. In this paper, firstly the aging effect due to bias temperature instability (BTI) is analyzed on circuits using 32-nm CMOS technology for soft errors. Secondly, we derive an accurate SER estimation model which can incorporate BTI impact, including the negative BTI impact on PMOS and the positive BTI impact on NMOS. This model computes the failures in time (FIT) rate of sequential circuits. Experiments are carried on ISCAS89 circuits, and two findings are discovered: (1) for ten years simulation operating time, the maximum SER difference can go up to 12.5 % caused by BTI impact; (2) the BTI-aware SER grows quickly during the early operating time, and grows slowly in the later years.