Cycle-Accurate Specification

Abstract

We now turn our attention to a higher level of modeling: cycle accurate, sometimes called scheduled behavior. At this level, a system is described in a clock-cycle by clock-cycle fashion, specifying the behavior that is to occur in each state. The term cycle-accurate is used because the values in the system are specified to be valid only at the time of the system's state change ~ at a clock edge. This chapter presents the cycle-accurate method of specification, overviews behavioral synthesis, and illustrates how to specify systems for design using behavioral synthesis. 7.1 Cycle-Accurate Behavioral Descriptions 7.1.1 Specification Approach Scheduled behavior is specified using always blocks, and "@(posedge clock);" statements are used to break the specification into clock cycles or states. Example 7.1 illustrates a scheduled behavioral description of a simple calculation. The module has ports for registers x, y, and the clock. Register i, a loop counter, is only used inside the module.