Design of non-volatile sram cell using memristor

Abstract

Emerging chip technologies employ power-off mode to diminish the power dissipation of chips. Non-volatile SRAM (NvSRAM) enables a chip to store the data during power–off modes. This non-volatility can be achieved through memristor memory technology which is a promising emerging technology with unique properties like low-power, high density and good-scalability. This paper provides a detailed study of memristor and proposes a memristor based 7T2M NvSRAM cell. This cell incorporates two memristors which store the bit information present in the 6T SRAM Latch, and a 1T switch which helps to restore the previously written bit in situations of power supply failures, thereby making the SRAM non-volatile.