Very short critical path implementation of AES with direct logic gates

Abstract

A lot of improvements and optimizations for the hardware implementation of AES algorithm have been reported. These reports often use, instead of arithmetic operations in the AES original, those in its isomorphic tower field and. This paper focuses on which provides higher-speed arithmetic operations than. In the case of adopting, not only high-speed arithmetic operations in but also high-speed basis conversion matrices from the to should be used. Thus, this paper improves arithmetic operations in with Redundantly Represented Basis (RRB), and provides basis conversion matrices with More Miscellaneously Mixed Bases (MMMB). © Springer-Verlag Berlin Heidelberg 2012.