Phase lock loop–based algorithms for DSTATCOM to mitigate load created power quality problems

Abstract

This paper describes about implementation of phase-locked loop (PLL)–based control algorithms for distribution static compensator (DSTATCOM) used to mitigate power quality issues due to unbalanced and non-linear load. Three control algorithms based on moving average filter PLL (MAF-PLL), double second order generalized integrator PLL (DSOGI-PLL), and adaptive filter with frequency estimation loop PLL (AFFEL-PLL) are used in this paper. These are more suitable to mitigate the power quality problems created by non-linear and unbalanced loads in distribution system. The reason behind selection in this application is explained as follows. The MAF-PLL has great filtering quality with less computational burden on processor which is verified using total harmonic distortion (THD) performance. AFFEL-PLL has variable integral gain that prevents large phase jump during frequency drift and load transient condition, this gives fast response. DSOGI-PLL uses both orthogonal components and prevents oscillatory error and gives more stable operation. The MAF-PLL and AFFEL-PLL uses only quadrature axis “q” component for reduction of phase error and detection of theta. To mitigate power quality issues, continuous monitoring of AC grid system is required, which provide information in terms of frequency, phase, and fundamental voltage magnitude. Out of all, the phase detecting methods using PLL is standard method to extract such information. All the PLLs mentioned here extract the required grid information. Further, DSOGI-PLL converts the distorted three-phase load current into respective orthogonal components. All the control algorithms mentioned are implemented using MATLAB and performance of most effect algorithm is recorded in laboratory environments.