Abstract
This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.
Cite
CITATION STYLE
Cantó, E., Moreno, J. M., Cabestany, J., Lacadena, I., & Insenser, J. M. (2000). Implementation of virtual circuits by means of the FIPSOC devices. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1896, pp. 87–95). Springer Verlag. https://doi.org/10.1007/3-540-44614-1_10
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