This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.
CITATION STYLE
Ishihara, T. (2010). A multi-performance processor for reducing the energy consumption of real-time embedded systems. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E93-A(12), 2533–2541. https://doi.org/10.1587/transfun.E93.A.2533
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