Systolic array architecture for two-dimensional discrete fourier transform

Abstract

This paper considers a formally derived architecture of a systolic processor which directly executes the algorithm of two-dimensional N1 × N2 -point DFT. The systolic processor contains a N1 × N2 -array of orthogonally-connected processor elements of the same type and carries out O(N1 N2 (N1 + N2)) complex operations of the algorithm in the time O(N1 + N2). The described design solution meets basic implementation requirements of VLSI-based hardware.