KL_GA: an application mapping algorithm for mesh-of-tree (MoT) architecture in network-on-chip design

Abstract

As the very large-scale integrated circuit designs enter the deep sub-micron era, many-core processors are regarded as promising architectures to keep up with the Moore’s law. To provide effective communications between the on-chip components, network-on-chip was proposed as a new paradigm that exhibits better scalability than the traditional buses. There have been previous researches on application mappings to reduce the power consumption, the network latency and the network area overhead. However, some of the previous proposed algorithms such as the Kernighan–Lin algorithm (KL) and some genetic algorithms (GA) have the problem of finding the local best result instead of a global optimal solution. In this paper, we propose a novel application mapping algorithm for the mesh-of-tree network topology, called KL_GA algorithm. Our proposed algorithm takes the advantage of both the Kernighan–Lin algorithm and genetic algorithms to reduce the overall communication cost. Our KL_GA algorithm first generates a mapping solution using a KL-based method. In order to avoid the appearance of premature phenomena, we next apply a GA-based algorithm to get rid of the population trapped in the local optimum and re-generate a new population. Our evaluations show that, compared to the random mapping algorithm, our KL_GA algorithm saves the power by 21.6 % and reduces the network latency by 16.3 % on the average.