Very Low Power High-Frequency Floating Point FPGA PID Controller

Abstract

In this work, we present the design and implementation of a floating-point Proportional-Integral-Derivative (PID) controller accelerator which achieves a high rate of 637 K samples per second at 20 mW of power consumption, implemented on a Lattice UP5K FPGA. Our system delivers over 70 × the performance compared to a microprocessor with comparable size and power constraints, and 5 × the power efficiency compared to a larger and more capable ARM Cortex-M4F with hardware floating-point operators. We achieve such high performance using a systolic array design using simplified hardware floating-point operators implemented using embedded DSP blocks on a low-power FPGA. We support simple handling of complex reference such as sinusoidal signals by storing the reference as a time series in on-chip block RAM. The level of high performance, low power, and small size we achieve is necessary for our target application of micro, or insect-scale robotics.