A short loop queue design for reduction of power consumption of Instruction-Fetching based on the dynamic branch folding technique

Abstract

On the basis of analyzing the characteristics of short loop instructions in embedded processors, this paper proposes a short loop instruction queue technique for reducing the power consumption of instruction fetching. By means of adding an instruction queue to store the short loop instruction between the fetch stage and the decode stage of the processor pipeline and dynamic detection circuits so as to detect the short loop instruction, this technique can reduce the delay resulting from the loop instruction and thus eliminate unnecessary access to the cache so as to reduce the power consumption of instruction fetching. Our experiments show that an average 16.7 % power saving can be achieved in instruction fetching without any performance degradation.