Significant reductions in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. With truncated multiplication, the less significant columns of the multiplication matrix are eliminated and correction terms are added to keep the total error to less than one unit in the last place. The truncated multiplication techniques presented in this paper are applied to FPGA parallel multipliers, and can be used in conjunction with a number of other performance enhancing techniques, such as pipelining, Booth encoding, and device specific optimizations to increase the effectiveness of device mapping, placing, and routing.
CITATION STYLE
Wires, K. E., Schulte, M. J., & McCarley, D. (2001). FPGA resource reduction through truncated multiplication. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2147, pp. 574–583). Springer Verlag. https://doi.org/10.1007/3-540-44687-7_59
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