Wafer level chip scale packaging

Abstract

Wafer Level Packaging (WLP) based on redistribution is the key technology which is evolving to System in Package (SiP) and Heterogeneous Integration (HI) by 3-D packaging using Through Silicon Vias (TSV). Materials and process technologies are key for a reliable WLP. It is not only the choice for the right polymer or metal but the interfaces could be even more critical like under bump metallurgy or the adhesion of polymers. This chapter focuses on the materials and processes for WLP which are the basic for all new 3-D integration technologies. © 2009 Springer-Verlag US.