Technology and Design of Classical and Heterojunction Back Contacted Silicon Solar Cells

Abstract

Ever since the first proposal of Interdigitated Back Contact (IBC) silicon solar cells in 1975, this type of cell has been under development as a means to reach high energy conversion efficiencies. Since no metal contacts are present on the front of the cell, IBC cells in general have a high generated current density (Jsc). Apart from this obvious advantage, IBC cells also have advantages related to the integration in modules. The series interconnection between various cells can be done at module level, without the need for connecting the front of one cell to the rear of the next one, as is the case in two-side contacted cells. IBC solar cell efficiencies of 21 to 24 percent have been shown on large area industrially produced cells. Another successful high efficiency concept is the heterojunction emitter solar cell, where the junctions are realized by application of intrinsic and doped amorphous silicon (a-Si) layers on high quality mono-crystalline silicon bulk material. The cells realized with a-Si heterojunctions have high open-circuit voltage values thanks to the excellent passivating properties of the a-Si layers. Combining the IBC concept with heterojunction junctions using thin high quality substrates has the potential of reaching solar cell efficiencies over 25 percent. Classical IBC cells have been studied for many years. Some of the more important aspects include substrate quality, front and rear surface passivation, rearjunction design and design and structure of the metallization. In literature several types of IBC cells have been reported, where a large variety of processes are described utilizing technologies ranging from lab-scale to industrially applicable methods. In recent years IBC research has focused on development of low cost and industrial technologies suited for IBC cell production on large scale and exploring the way towards the use of thinner and thinner silicon substrates. Although results have been reported on heterojunction emitter structures for almost twenty years, it is only in the last five years that the implementation of the heterojunction emitter at the rear of the wafer has received much research interest. For this reason, many of the papers that have been published on this subject display cell structures and processing that are not optimized, and are typically fabricated on small area cells. Efficiencies currently are in the order of 12 to 16 percent. These proof-of-concept cells are just the start of a new development and a rapid evolution in the efficiencies is expected in the months and years ahead.