FPGAs implementation of a digital IQ demodulator using VHDL

Abstract

This paper presents the implementation of a digital IQ demodulator in FPGA devices. A DSP-based algorithm representing the demodulator was described in behavioural VHDL, which was used for simulation at the functional level. During the simulation, not only the functions were verified, the finite word-length effect and the coefficient quantization error were investigated as well. The VHDL description was then synthesised by using behavioural synthesis software. Different architectures were explored and manual partition was done on the behavioural description so that the selected architecture could fit into five reprogrammable FPGA devices. Postrouting simulation and hardware testing were carried out to verify the final implementation.