On the functional test of Branch Prediction Units based on the branch history table architecture

Abstract

Branch Prediction Units (BPUs) are commonly used in pipelined processors, since they can significantly decrease the negative impact of branches in superscalar and RISC architectures. Traditional solutions, mainly based on scan, are often inadequate to effectively test these modules: in particular, scan does not represent a viable solution when Incoming Inspection or on-line test are considered. Functional test may stand as an effective solution in these situations, but requires effective algorithms to be available. In this paper we propose a functional approach targeting the test of BPUs based on the Branch History Table (BHT) architecture; the proposed approach is independent on the specific implementation of the BPU, and is thus widely applicable. Its effectiveness has been validated on a BPU resorting to an open-source computer architecture simulator and to an ad hoc developed HDL testbench. Experimental results show that the proposed method is able to thoroughly test the BPU, reaching complete static fault coverage with reasonable requirements in terms of test program size and execution time. © 2012 IFIP International Federation for Information Processing.