A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architecture

Abstract

Abstract From the final years of the twentieth century, nanotechnology has emerged in various forms with the promise of enabling new applications among a variety of disciplines. The field of digital integrated circuit design is one such discipline within which researchers are continually seeking ways of leveraging novel nanoscale technologies to develop next generation circuits and architectures. A major motivating factor for this research is the expected end of device scaling for more conventional bulk silicon technologies, specifically CMOS. Many nanoscale devices have been proposed as replacements for the MOS transistor, from spintronic devices to molecular switches, each coming with their own pros and cons. In fact, it can be argued that, for many applications, nanoscale CMOS remains as viable as any other nanoelectronic device family, at least in the near term. Thus, this chapter explores the concept of hybrid CMOS-nano circuit design for leveraging the best of scaled CMOS alongside of the best of novel nanoelectronics. This is accomplished by describing some novel nanoelectronic devices and comparing them to the traditional MOSFET. After some discussion about circuit level considerations when integrating CMOS with nanoelectronics, a hybrid CMOS-nano field programmable gate array (FPGA) based on nanoscale hysteretic switches and negative differential resistance (NDR) is also described and explored in detail.