Abstract
The amount of data transfer required by (parallel) applications can be of significant importance for performance due to bandwidth limitations in real systems. For intra-node, data transfer refers to memory accesses, and usually, cache miss counts are used for performance analysis. However, they cannot explicitly show utilization of links and buses in the memory hierarchy. In this paper, we propose an explicit visualization of the bandwidth requirements of applications within memory hierarchies. This is based on a machine model without bandwidth limits. We show its usefulness within the context of a simple 2D stencil iterative solver, with and without cache optimization applied. © 2014 Springer-Verlag Berlin Heidelberg.
Cite
CITATION STYLE
Weidendorfer, J. (2014). Data transfer requirement analysis with bandwidth curves. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 8374 LNCS, pp. 607–616). Springer Verlag. https://doi.org/10.1007/978-3-642-54420-0_59
Register to see more suggestions
Mendeley helps you to discover research relevant for your work.
