Integration of reconfigurable hardware into system-level design

Abstract

In this paper, we present a design methodology for high-performance systems based on heterogeneous models. These models contain functions, that are implemented with reconfigurable hardware components. During the stepwise refinement-based design process, a hardware/software system prototype is developed. In the process, we start with a conceptual, implementation independent design at the system-level. Hereby, we employ the commercial Cadence Cierto VCC (Virtual Component Codesign) tool, which allows to model the system with an architectural-, behavioral-, timing-, and performance view. Standard C or C++ serve as modeling language and description of the software-only system and the refinement process. During refinement, selected blocks are evaluated and transformed in stepwise fashion to hardware using Handel-C for subsequent mapping to Xilinx® Virtex 1000E FPGAs attached to a standard PC. The hardware implementations on reconfigurable logic are seamlessly integrated into the VCC environment by stub modules, which perform the hardware/software interfacing and communication via shared memory DMA transfers. This paper presents the methodology and illustrates it using an example of a Viterbi encoder/decoder. © Springer-Verlag Berlin Heidelberg 1998.