Abstract
Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrating the capabilities of the methodology as well highlighting the impacts of the two degradations modes. © Springer-Verlag Berlin Heidelberg 2007.
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CITATION STYLE
Parthasarathy, C. R., Bravaix, A., Guérin, C., Denais, M., & Huard, V. (2007). Design-in reliability for 90-65nm CMOS nodes submitted to hot-carriers and NBTI degradation. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4644 LNCS, pp. 191–200). Springer Verlag. https://doi.org/10.1007/978-3-540-74442-9_19
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