Abstract
We describe a hybrid formal hardware verification tool that links the HOL interactive proof system and the MDG automated hardware verification tool. It supports a hierarchical verification approach that mirrors the hierarchical structure of designs. We obtain advantages of both verification paradigms. We illustrate its use by considering a component of a communications chip. Verification with the hybrid tool is significantly faster and more tractable than using either tool alone.
Cite
CITATION STYLE
Kort, I., Tahar, S., & Curzon, P. (2001). Hierarchical verification using an MDG-HOL hybrid tool. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2144, pp. 244–258). Springer Verlag. https://doi.org/10.1007/3-540-44798-9_21
Register to see more suggestions
Mendeley helps you to discover research relevant for your work.
