Optimum performance of carbon nanotube field-effect transistor based sense amplifier D flip-flop circuits

Abstract

The data storage logic circuit consumes a huge amount of power in any semiconductor memory design. Continuous scaling introduces unreliable memory read/write operations, so alternate solutions need to be explored. Carbon nanotube field-effect transistors have the ability to work on ultralow power applications. Power and delay minimization are the current trending issues beyond CMOS digital logic design. This paper presents a detailed analysis of various reported Sense amplifier D flip-flop (SAFF) designs in order to select the one which is most suitable for high-performance applications. The D flip-flop circuits have been simulated using 32 nm CMOS technology and compared with 32 nm CNFET based D flip-flops output results. Semi-dynamic flip-flop has speed benefit and low power sense amplifier flip-flop (LPSAFF) has energy advantage. Also, the effect of variation in diameter and width of CNT’s has been analyzed in this paper to select the best topology for ultralow power applications.