Channel estimation for advanced 5G/6G use cases on a vector digital signal processor

Abstract

As we target implementations of very high-end () specifications and look towards the future, it becomes apparent that the stringent execution deadlines in physical layer (PHY) procedures are hard to satisfy using traditional algorithms optimised for high throughput. Hence, if the designer adheres to the same throughput efficient algorithm and simply scales up the hardware (HW), the device effectively becomes overprovisioned, costing more than it would if the designer opted for a latency efficient algorithm. However, latency efficient algorithms cost more operations per transmitted data item, and therefore consume more power compared to throughput efficient algorithms. Consequently, if the designer opts for latency efficient algorithms, the implementation would be power inefficient for all but the latency-critical use cases. We identify the use-cases where these problems occur in the channel estimation (CE) PHY procedure and propose a software (SW) implementation that can dynamically switch between latency and throughput efficient algorithms and thereby avoid both unnecessary HW overprovisioning and excess power consumption. In this article we demonstrate this with an example implementation of CE for the high-end and quantify the benefits of this approach.