Circuit analysis of the memristive stateful implication gate

Abstract

A recently published memristive stateful implication (IMP) gate circuit is analysed with confirmation that it cannot achieve the full resistance switching of the output memristor in case both input memristors of the IMP gate are in the OFF resistance state. The initial parameter conditions for the IMP gate are derived, and the minimum resistance of the output memristor achievable is yielded. The HSPICE simulation confirms that a resistance refreshing scheme is indispensable for the IMP gate to function properly. © The Institution of Engineering and Technology 2013.