Efficient precharge-free CAM match-line architecture design for low power

Abstract

Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and searches that data parallel within a single clock cycle. Conventional CAM operates in three phases which are writing the binary data in the memory, pre-charging, and evaluating the match line (ML). Recently, it is identified that CAM with precharge ML consumes more power due to the short circuit current path. To overcome this problem, here, we proposed CAM architecture without applying precharge to ML which helps to operate CAM with low power and high performance. The precharge-free CAM works on two stages writing and evaluation. This paper compares conventional precharge-based ML architecture like NOR CAM and master-slave CAM of 1 (word) × 8 (bits) with a proposed design for power consumption at different mismatches. Simulations results show that when compared to conventional designs, the proposed design minimizes approximately from 86 to 88% of average power.