Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.
CITATION STYLE
Zhang, H., Wei, B., Lu, Y., & Shu, J. (2019). SIRM: Shift Insensitive Racetrack Main Memory. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 11783 LNCS, pp. 355–360). Springer. https://doi.org/10.1007/978-3-030-30709-7_33
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