A multi-level routing scheme and router architecture to support hierarchical routing in large network on chip platforms

Abstract

The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free routing. We propose a 2-level routing scheme, which is not only efficient, but also enables co-existence of algorithmic and table-based implementation in one router. Synthesis results show that a 2- level hierarchical router design for an 8x8 NoC, can reduce area and power requirements by up to ~20%, as compared to a router for the flat network. This work also proposes a new possibility for increasing the number of nodes available for subnet-to-subnet interfaces. Communication performance is evaluated for various subnet interface set-ups and traffic situations. © 2011 Springer-Verlag Berlin Heidelberg.