Implementation of fractional-order operators on field programmable gate arrays

Abstract

Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. The fundamental operator sa is realized via two different approximations. By applying the binomial expansion, the fractional operator is realized as a high-order finite impluse reform (FIR) filter mapped onto a pipelined multiplierless architecture. An IIR approximation is also developed as a parallel combination of first-order filters using the embedded hardware multipliers available on FPGAs. Unlike common fixed-point digital implementations in which all filter coefficients have the same word length, our method quantizes each coefficient using a custom word length chosen in accordance with the filter's sensitivity to perturbations in the coefficient's value. The systems are built based on Xilinx's low-cost Spartan-3 FPGA. They show that the FPGA is an effective platform on which to implement high quality, high throughput approximations to fractional-order systems that are low in cost and require only short design times. © 2007 Springer.