Technological Crossroads: Silicon or III–V for Future Generation Nanotransistors

Abstract

We present the results of a three-dimensional, self-consistent ballistic quantum mechanical simulation of an indium arsenide (InAs) quantum wire metal oxide semiconductor field effect transistor (MOSFET) with channel lengths of approximately 10 nm. We find that these devices exhibit exceptional lon/Ioff ratio, reasonable subthreshold swing and reduced threshold voltage variation. Finally, we compare the performance of the 10 nm InAs tri-gate device to a similar silicon device. We find that, when a suitable gate material is chosen, the InAs devices perform comparably to silicon devices in the ballistic limit. While the prospects look promising for SNWTs, there are also other materials under consideration for next generation transistor applications. Within the last few years, there has been a renewed interest in the use of III-V materials instead of silicon for devices. This is mainly due to the fact that the III-V based transistors have the possibility of boasting much higher channel mobilities when compared to that of silicon. In this paper, we compare the performance of similar InAs and silicon nanowire transistors. In Fig. 1, we display a schematic of the device geometry used for an InAs MOSFET. The thickness of the InAs layer is 9.09 nm. The source and drain of the device are n-typc with a doping density of 6 x 10 cm"^ while the channel of the device is considered to be /?-type, but un-doped. The gate material is assumed to be platinum and the gate oxide on each side is composed of 1 nm of hafnium oxide (Hf02). Underneath the device, we have assumed a generic insulating substrate. We model the device using recursive scattering matrices [1] where self-consistency is accelerated using the modified Broyden's method [2].