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Speeding Up Verification of RTL Designs by Computing One-to-One Abstractions with Reduced Signal Widths

  • Johannsen P
  • Drechsler R
DOI: 10.1007/978-0-387-35597-9_31
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Johannsen, P., & Drechsler, R. (2002). Speeding Up Verification of RTL Designs by Computing One-to-One Abstractions with Reduced Signal Widths (pp. 361–374). https://doi.org/10.1007/978-0-387-35597-9_31

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