Compiler and system techniques for SoC distributed reconfigurable accelerators

Abstract

To answer new challenges, systems on chip need to gain flexibility and FPGAS need to gain structure. We propose a general framework for SoC architectures and software tools in which different kind of processing units are programmed at high level. We show a reconfigurable unit suitable for this framework and we draw the outline of a super-compiler able to address such an architecture. © Springer-Verlag Berlin Heidelberg 2004.