Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array

Abstract

Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times. © Springer-Verlag Berlin Heidelberg 2004.