Tuna Swarm Optimization with 3D-chaotic map and DNA encoding for image encryption with lossless image compression based on FPGA

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Abstract

Images and video-based multimedia data are growing rapidly due to communication network technology. During image compression and transmission, images are inevitably corrupted by noise due to the influence of the environment, transmission channels, and other factors, resulting in the damageand degradation of digital images. Numerous real-time applications, such as digital photography, traffie monitoring, obstacle detection, surveillance applications, automated character recognition, etc are affected by this information loss. Therefore, the efficient and safe transmission of data has become a vital study area. In this research, an image compression-encryption system is proposed to achieve security with low bandwidth and image de-noising issues during image transmission. The Chevrolet transformation is proposed to improve image compression quality, reduce storage space, and enhance denoising. A 3D chaotic logistic map with DNA encoding and Tuna Swarm Optimization is employed for innovative image encryption. This optimization approach may significantly increase the image's encryption speed and transmission security. The proposed system is built using the Xilinx system generator tool on a field-programmable gate array (FPGA). Experimental analysis and experimental findings show the reliability and scalability of the image compression and encryption technique designed. For different images, the security analysis is performed using several metrics and attains 32.33 dB PSNR, 0.98 SSIM, and 7.99721 information entropy. According to the simulation results, the implemented work is more secure and reduces image redundancy more than existing methods.

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CITATION STYLE

APA

Hebbale, S. B., Akula, V. S. G., & Baraki, P. (2023). Tuna Swarm Optimization with 3D-chaotic map and DNA encoding for image encryption with lossless image compression based on FPGA. International Journal of Electrical and Computer Engineering Systems, 14(1), 59–72. https://doi.org/10.32985/ijeces.14.1.7

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